- Title
- Bifurcations in iterative decoding and root locus plots
- Creator
- Kellett, C. M.; Weller, S. R.
- Relation
- IET Control Theory and Applications Vol. 2, Issue 12, p. 1086-1093
- Publisher Link
- http://dx.doi.org/10.1049/iet-cta:20080090
- Publisher
- The Institution of Engineering and Technology
- Resource Type
- journal article
- Date
- 2008
- Description
- A class of error correction codes called ‘low-density parity-check (LDPC)’ codes have been the subject of a great deal of recent study in the coding community as a result of their ability to approach Shannon’s fundamental capacity limit. Crucial to the performance of these codes is the use of an ‘iterative’ decoder. These iterative decoders are effectively high-dimensional, nonlinear dynamical systems and, consequently, control-theoretic tools are useful in analysing such decoders. The authors describe LDPC codes and the decoding algorithm and make a connection between the fixed points of the decoding algorithm and the wellknown root locus plot. Through two examples of LDPC codes, the authors show that the root locus plot visually captures the bifurcation behaviour of iterative decoding that occurs at the signal-to-noise ratio predicted by Shannon’s noisy channel coding theorem.
- Subject
- codes; low-density parity-check (LDPC); root locus plot; signal-to-noise ratio
- Identifier
- uon:5580
- Identifier
- http://hdl.handle.net/1959.13/43481
- Identifier
- ISSN:1751-8644
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